Breaking the GaN material limits with nanoscale vertical polarisation super junction structures: A simulation analysis

This is the first report on the numerical analysis of the performance of nanoscale vertical superjunction structures based on impurity doping and an innovative approach that utilizes the polarisation properties inherent in III-V nitride semiconductors. Such nanoscale vertical polarisation super junction structures can be realized by employing a combination of epitaxial growth along the non-polar crystallographic axes of Wurtzite GaN and nanolithography-based processing techniques. Detailed numerical simulations clearly highlight the limitations of a doping based approach and the advantages of the proposed solution for breaking the unipolar one-dimensional material limits of GaN by orders of magnitude

Evaluation of gate drive circuit effect in cascode GaN-based application

This work evaluates the influence of gate drive circuitry to cascode GaN device’s switching waveforms. This is done by comparing three PCBs using three double-pulse-test (DPT) with different gate driving loop design. Among important parasitic elements, source-side inductance shows a significant impact to gate-source voltage waveform. A simulation model based on experimental measurement of the cascode GaNFET used in this work is modified by author. The simulation model is implemented in a synchronous buck converter topology and hereby to assess the impact of gate driving loop of cascode GaN device in both continuous conduction mode (CCM) and critical conduction mode (CRM). Apart from simulation, a synchronous buck converter prototype is presented for experimental evaluation, which shows a 99.15% efficiency at 5A under soft-switching operation (CRM) with a 59ns dead-time

Impact of poly-crystalline diamond within power semiconductor device modules in a converter

This paper presents the finding of thermal characterization of polycrystalline diamond for power semiconductor device modules in a converter. Comparisons of measured thermal performance of two diamond demonstrators, consisting of metalized diamond tiles attached to aluminum and copper forced air cooled heat sinks; show that power dissipation can be increased from 278W to 535W when compared to commercial products operating at a case temperature of 100°C and a maximum junction temperature of 175°C. Detailed converter simulations of a two level three-phase inverter driving a 15kW permanent magnet machine shows that using diamond can increase active power density from 13kW/kg to 17kW/kg at a coolant temperature of 100°C and a flowrate of 6 liters per minute

Analysis of drain current saturation behaviour in GaN polarisation super junction HFETs

The magnitude of saturation current in a power device significantly impacts its short-circuit capability. In conjunction with the unprecedented miniaturisation that gallium nitride (GaN) offers, there is a compelling rationale to examine this critical parameter in GaN transistors for thermally stable and reliable power converter applications. This study presents a comprehensive analysis of the physical behaviour that yields intrinsically low drain current saturation in GaN polarisation super junction heterojunction field-effect transistors (PSJ HFETs). The analysis in this work has been performed using electrical characterisation data of conventional and PSJ HFETs, supported by physics-based two-dimensional device simulations. Insight is gained on the differing device architecture-dependent mechanisms that determine the magnitude of drain current density in both types of devices when biased in the saturation region

The 2018 GaN Power Electronics Roadmap

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here

Analysis of Voltage Source Converters Under DC Line-to-Line Short-Circuit Fault Conditions

In this paper, the reaction of Voltage Source Converters (VSC) to short-circuit fault conditions across the DC terminals is analyzed. Multiple stages of the fault are identified, with the equivalent circuits generated, and analytical expressions for all voltages and currents of interest at each stage derived. The analyses presented provide detailed characterization of the converter circuit under this condition, including the effects of various circuit parameters on the fault response. The findings are validated against simulations, as well as experimentally using a single-channel replica of a dual-channel 100kW rated motor drive designed and built for aerospace application

Reliability Study and Modelling of IGBT Press-Pack Power Modules

The IGBT press-pack provides low inductance and simple module stack for high power and high voltage applications. In this work, the reliability of IGBT Press-Pack power modules is experimentally tested under RBSOA conditions to investigate their limitation and current scalability. The internal current distribution is analyzed by detailed 3D FEM simulation. This work reveals that the uneven distribution of current density is caused by different impedance in each IGBT die current conducting path, due to skin and proximity effects during switching transient. Stray and mutual inductances also affect current paths depending upon the location of IGBT within the package. The unbalanced switching times become larger as the package size increases with more parallel configured IGBTs. By extracting the FEM data into the proposed circuit model, the electrical performance will be discussed in detail

Analysis of a Clustered IGBT and Silicon Carbide MOSFET Hybrid Switch

In this paper, a parallel arrangement of a silicon MOS-gated thyristor structure and a silicon carbide Power MOSFET is proposed and experimentally demonstrated for the first time. Experimental results show that the hybrid switch exhibits low conduction losses at low current levels as well as large current-carrying capability at high current levels. In addition, compared to Clustered IGBT structure, the hybrid switch exhibits a 43% reduction in Eoff without any increase in Vce(sat) at 150°C